control reg 4

Macros
#define	C6DOFIMU15_DEC_TS_BATCH_1   0x40
#define	C6DOFIMU15_DEC_TS_BATCH_8   0x80
#define	C6DOFIMU15_DEC_TS_BATCH_32   0xC0
#define	C6DOFIMU15_ODR_T_BATCH_1_6_HZ   0x10
#define	C6DOFIMU15_ODR_T_BATCH_12_5_HZ   0x20
#define	C6DOFIMU15_ODR_T_BATCH_52_HZ   0x30
#define	C6DOFIMU15_FIFO_DIS   0x00
#define	C6DOFIMU15_FIFO_ST_WHEN_FULL   0x01
#define	C6DOFIMU15_CONT_TO_FIFO   0x03
#define	C6DOFIMU15_BYP_TO_CONT   0x04
#define	C6DOFIMU15_CONT_MODE   0x06
#define	C6DOFIMU15_BYP_TO_FIFO   0x07

Detailed Description

Macro Definition Documentation

C6DOFIMU15_BYP_TO_CONT

#define C6DOFIMU15_BYP_TO_CONT   0x04

C6DOFIMU15_BYP_TO_FIFO

#define C6DOFIMU15_BYP_TO_FIFO   0x07

C6DOFIMU15_CONT_MODE

#define C6DOFIMU15_CONT_MODE   0x06

C6DOFIMU15_CONT_TO_FIFO

#define C6DOFIMU15_CONT_TO_FIFO   0x03

C6DOFIMU15_DEC_TS_BATCH_1

#define C6DOFIMU15_DEC_TS_BATCH_1   0x40

C6DOFIMU15_DEC_TS_BATCH_32

#define C6DOFIMU15_DEC_TS_BATCH_32   0xC0

C6DOFIMU15_DEC_TS_BATCH_8

#define C6DOFIMU15_DEC_TS_BATCH_8   0x80

C6DOFIMU15_FIFO_DIS

#define C6DOFIMU15_FIFO_DIS   0x00

C6DOFIMU15_FIFO_ST_WHEN_FULL

#define C6DOFIMU15_FIFO_ST_WHEN_FULL   0x01

C6DOFIMU15_ODR_T_BATCH_12_5_HZ

#define C6DOFIMU15_ODR_T_BATCH_12_5_HZ   0x20

C6DOFIMU15_ODR_T_BATCH_1_6_HZ

#define C6DOFIMU15_ODR_T_BATCH_1_6_HZ   0x10

C6DOFIMU15_ODR_T_BATCH_52_HZ

#define C6DOFIMU15_ODR_T_BATCH_52_HZ   0x30